TOKYO ELECTRON 1D10-203699-11 Focus Ring – PW3-32/900

TOKYO ELECTRON 1D10-203699-11 — Focus Ring for PW3-32/900 Plasma Process Chamber

The TOKYO ELECTRON 1D10-203699-11 is a precision-machined focus ring (also catalogued under alternate P/N 119151-01) engineered specifically for the PW3-32/900 plasma processing platform. Within a capacitively coupled plasma (CCP) etch chamber, the focus ring occupies the outermost annular position on the electrostatic chuck (ESC) assembly. Its primary function is to extend the plasma sheath uniformly across the wafer edge, preventing the characteristic roll-off of etch rate and ion flux that would otherwise degrade critical-dimension (CD) uniformity at the die periphery. Secondary functions include mechanical protection of the ESC dielectric surface and thermal boundary management at the wafer perimeter.

In the PW3-32/900 architecture, the focus ring interfaces directly with the lower electrode RF circuit. As the ring material erodes through ion bombardment over its qualified service life, the sheath geometry shifts progressively outward, causing measurable etch-rate non-uniformity (ERU) drift. TEL’s process qualification data for this platform specifies a replacement threshold based on cumulative RF hours and erosion depth, making part traceability and OEM dimensional conformance non-negotiable for yield-sensitive production environments.

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Technical Parameters

Hardware Logical Analysis

The 1D10-203699-11 focus ring operates within a dual-frequency RF excitation environment. The PW3-32/900 platform applies a high-frequency source power (13.56 MHz) to sustain plasma density and a low-frequency bias power (typically 2 MHz) to the lower electrode to control ion energy distribution function (IEDF). The focus ring, positioned concentrically around the wafer on the lower electrode, is electrically floating or weakly coupled depending on the chamber configuration. This floating potential allows the ring to self-bias under ion bombardment, which in turn shapes the local sheath potential at the wafer edge.

EMC and RF Shielding Geometry: The annular geometry of the 1D10-203699-11 is machined to tight concentricity tolerances (typically ±0.05 mm on inner diameter) to prevent asymmetric plasma perturbation. Any eccentricity in the ring seat introduces azimuthal non-uniformity in the RF sheath, which manifests as angular etch-rate variation across the wafer — a defect mode that is difficult to distinguish from process drift without detailed wafer mapping. The OEM dimensional specification eliminates this variable.

Erosion Mechanics and Replacement Logic: Under fluorine-based etch chemistries (e.g., CF₄/O₂, SF₆/C₄F₈), silicon focus rings erode at a rate proportional to ion flux density and bias power. TEL’s PM schedule for the PW3-32/900 defines a maximum erosion depth (typically 1.0–2.0 mm from the original top surface) beyond which sheath geometry deviation exceeds the process window. Quartz variants exhibit lower etch selectivity relative to silicon but offer superior thermal stability in high-power deposition processes. Material selection must align with the specific process chemistry and power regime in use.

Thermal Management at the Wafer Edge: The focus ring also functions as a thermal boundary element. In helium-backside-cooled ESC configurations, the ring’s thermal conductivity and contact geometry influence the radial temperature gradient at the wafer edge. Silicon rings (thermal conductivity ≈ 150 W/m·K) provide superior edge cooling compared to quartz (≈ 1.4 W/m·K), which is a critical consideration in thermally sensitive etch processes where photoresist selectivity is temperature-dependent.

System Integration Benefits

• Plasma Sheath Uniformity: OEM-dimensioned ring maintains the designed sheath geometry across the full wafer diameter, preserving within-wafer uniformity (WiWU) targets specified in the TEL process recipe.
• CD Uniformity at Die Edge: Consistent ion flux at the wafer periphery reduces edge-die yield loss, directly improving gross die per wafer (GDW) metrics in high-density device layouts.
• Predictable PM Scheduling: TEL-qualified RF-hour service life enables deterministic preventive maintenance planning, reducing unplanned chamber downtime and associated production schedule disruption.
• Process Recipe Stability: Replacing with the OEM part number eliminates the need for recipe re-qualification that would be required after installing a dimensionally non-conformant aftermarket ring.
• Contamination Control: High-purity substrate material (≥ 5N silicon) minimizes metallic contamination contribution to the process environment, protecting device electrical characteristics in gate-oxide and contact-etch applications.
• Lot Traceability: Full OEM lot documentation supports SEMI E10 equipment reliability reporting and internal quality management system (QMS) audit requirements.
• Reduced Particle Risk: Class 10-cleaned and double-bagged packaging protocol prevents particulate introduction during installation, a critical factor in sub-28 nm node processes where particle-induced defect density directly impacts yield.
• Dual-Frequency RF Compatibility: Verified dielectric and dimensional properties ensure stable floating-potential behavior under both 13.56 MHz and 2 MHz excitation, preventing anomalous arcing or sheath instability at the ring-wafer interface.

Quality Assurance & Global Logistics

Every TOKYO ELECTRON 1D10-203699-11 unit supplied through siemensplc.com is sourced from verified authorized distribution channels or factory-direct inventory. Pre-shipment inspection includes dimensional verification of inner diameter, outer diameter, and thickness against TEL OEM drawings; surface particle count inspection under cleanroom conditions; and visual examination for micro-cracks, chips, or surface contamination. A Certificate of Conformance (CoC) is available upon request for production-line quality records.

Logistics operations are managed from our warehouse in Xiamen, China. Standard international shipments are dispatched via DHL Express, FedEx International Priority, or UPS Worldwide Expedited, with typical transit times of 3–7 business days to major semiconductor manufacturing hubs in Taiwan, South Korea, the United States, Germany, and Singapore. For time-critical AOG (Aircraft on Ground equivalent) semiconductor line-down situations, same-day dispatch is available for in-stock units confirmed before 14:00 CST. All export documentation — including commercial invoice, packing list, and HS code classification — is prepared in compliance with Chinese customs regulations and destination-country import requirements.

Contact Information

Email: [email protected]
WhatsApp: +86 18359268345
Web: siemensplc.com
Location: Xiamen, China
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