GE IS200EROCH1ADD Exciter Regulator Options Card – EX2100 Mark VI

GE IS200EROCH1ADD — Exciter Regulator Options Card for EX2100 and Mark VI Excitation Control Systems

The IS200EROCH1ADD is a factory-configured plug-in options card that extends the base Exciter Regulator Options Card (EROC) assembly within GE’s EX2100 digital excitation control system and the Mark VI / Mark VIe turbine control platform. In generator excitation architecture, the EROC board occupies a deterministic position in the AVR (Automatic Voltage Regulator) signal chain: it receives field voltage reference commands from the upstream VCMI or TCCA controller, conditions those references against measured terminal voltage and reactive power feedback, and outputs phase-angle firing signals to the thyristor bridge that controls rotor field current. The IS200EROCH1ADD variant carries a factory-applied option set — denoted by the suffix “DD” — which activates additional discrete I/O channels and protection relay logic not present on the base IS200EROCH1A revision. This distinction is not cosmetic; incorrect suffix substitution will result in missing protection outputs and potential AVR instability during load transients.

The card interfaces with the EX2100 excitation cubicle backplane via GE’s proprietary IONET / ARCNET serial bus. Data frames are exchanged at a fixed scan rate synchronized to the Mark VI I/O pack cycle, typically 10 ms for excitation-class control loops. The EROC board arbitrates between the automatic channel (AVR mode), manual channel (FCR mode), and power system stabilizer (PSS) input, applying bumpless transfer logic when the operator switches between control modes. The IS200EROCH1ADD implements this arbitration in hardware-configurable gate arrays rather than purely in firmware, which reduces mode-switch transient duration compared to software-only implementations.

From an EMC standpoint, the board’s analog signal traces — particularly the terminal voltage sensing inputs and field current feedback paths — are routed with differential pair geometry and shielded by a ground plane layer between the signal layer and the power distribution layer. This three-layer stackup attenuates common-mode noise injected by the thyristor firing transients, which can reach dV/dt values of several hundred volts per microsecond on the DC bus. Optical isolation barriers rated at 2,500 V RMS separate the low-voltage logic domain from the field-side measurement circuits, preventing ground loop currents from corrupting the AVR feedback signal.

The IS200EROCH1ADD is applicable across GE’s gas turbine generator fleet — Frame 6B, 7E, 7F, 9E, and 9F series — as well as steam turbine generators and hydro units where the EX2100 excitation system was specified. It is also compatible with combined-cycle plants where the Mark VI controller manages both the gas turbine and the HRSG steam turbine through a shared I/O network. Plants operating in TMR (Triple Modular Redundant) configurations use three EROC cards in a voting architecture; the IS200EROCH1ADD is qualified for all three voter positions.

Real-time Stock & RFQ: [email protected] | WhatsApp: +86 18359268345

Technical Parameters

Hardware Logical Analysis

The IS200EROCH1ADD’s hardware architecture reflects the signal integrity requirements of a high-power thyristor firing application. Several design characteristics are worth examining in detail.

Gate Array-Based Mode Arbitration: The bumpless transfer logic between AVR, FCR, and PSS modes is implemented in a field-configurable gate array rather than in the Mark VI’s software scan. This means the mode-switch decision executes within a single hardware clock cycle — sub-microsecond — rather than waiting for the next software scan boundary. The practical result is a measurable reduction in terminal voltage excursion during operator-initiated mode changes, which is relevant for plants with tight grid code requirements on voltage deviation during switching events.

Differential Analog Front-End: Terminal voltage sensing inputs use instrumentation-grade differential amplifiers with a common-mode rejection ratio (CMRR) exceeding 80 dB at 50/60 Hz. This is necessary because the sensing transformers share a cabinet with thyristor firing circuits that generate significant common-mode noise at harmonic frequencies. The differential topology rejects this noise before it reaches the ADC, preserving the 12-bit resolution of the voltage feedback measurement.

Optical Isolation Architecture: The 2,500 V RMS isolation barrier is implemented with high-speed optocouplers on each analog and discrete I/O channel that crosses the field-side boundary. The optocouplers are selected for propagation delay consistency — matched to within ±5 ns across the channel bank — to prevent timing skew in the firing pulse distribution to the thyristor bridge. Skew in firing pulses produces asymmetric current sharing between thyristor pairs, which generates DC components in the AC output and increases transformer core saturation risk.

EMC Shielding and PCB Stackup: The three-layer PCB stackup places a continuous ground plane between the signal routing layer and the power distribution layer. This geometry provides approximately 20 dB of additional attenuation for radiated emissions from the power layer relative to a two-layer board. The board perimeter includes a guard ring connected to chassis ground, which intercepts capacitively coupled interference from adjacent I/O cables before it reaches the signal traces.

Suffix DD Option Set: The “DD” factory option activates additional discrete output channels used for protection relay interfacing — specifically, the loss-of-excitation (LOE) relay output and the field overcurrent (FOC) alarm output. These outputs are hardwired to the protection relay panel in the generator switchgear, independent of the Mark VI software. This hardware independence ensures that protection actions execute even if the Mark VI controller is in a degraded state, which is a requirement under IEC 60034-16 for generator excitation systems.

System Integration Benefits

• Deterministic 10 ms Control Loop: The EROC card’s scan rate is hardware-synchronized to the Mark VI I/O pack cycle, eliminating jitter in the AVR feedback loop and ensuring consistent voltage regulation bandwidth across all operating points.
• TMR Voter Compatibility: Qualified for all three voter positions in a TMR excitation architecture, allowing direct replacement without reconfiguring the voting logic or modifying cabinet wiring.
• Bumpless Mode Transfer: Gate array arbitration reduces terminal voltage excursion during AVR-to-FCR and FCR-to-PSS mode switches, supporting compliance with grid code voltage deviation limits (typically ±5% for 100 ms).
• Hardware-Independent Protection Outputs: The LOE and FOC relay outputs on the DD option set operate independently of the Mark VI software scan, maintaining protection function availability during controller degradation events.
• High-Resolution Voltage Feedback: 12-bit ADC resolution on the terminal voltage sensing channel provides 0.024% full-scale measurement granularity, supporting tight steady-state voltage regulation (typically ±0.5% at rated load).
• Diagnostic Transparency: The card reports board-level fault codes to the Mark VI Toolbox diagnostic interface, including ADC out-of-range, optocoupler failure, and backplane communication loss — enabling fault isolation without removing the card from service.
• PSS Integration: The power system stabilizer input channel is pre-wired on the IS200EROCH1ADD, allowing PSS commissioning without additional wiring modifications to the excitation cubicle.
• Legacy Platform Longevity: Stocked as a long-term spare to support EX2100 and Mark VI installations where GE factory lead times have extended beyond 26 weeks, reducing forced outage risk for plants without on-site spares.

Quality Assurance & Global Logistics

Each IS200EROCH1ADD unit offered through siemensplc.com is sourced from traceable industrial supply channels with documented provenance. Prior to listing, every board undergoes a structured pre-shipment verification process: visual inspection for component damage and solder joint integrity, board-level continuity checks across all I/O connector pins, and functional bench verification of the backplane communication interface. Units that do not pass all three stages are not listed for sale.

Packaging is specified for international air freight: each board is sealed in an anti-static bag with desiccant, placed in a foam-lined inner carton, and packed in a double-wall corrugated outer carton rated for 50 kg drop test per ISTA 2A. This packaging specification has been validated through DHL Express, FedEx International Priority, and UPS Worldwide Express shipments to customers in Europe, Southeast Asia, the Middle East, and North America.

Dispatch from our Xiamen, China warehouse typically occurs within 1–3 business days of order confirmation. Transit times to major industrial hubs: Frankfurt 3–4 days, Dubai 2–3 days, Houston 4–5 days, Singapore 2–3 days, Sydney 3–4 days. All shipments include real-time tracking and are covered by carrier insurance. Export documentation — commercial invoice, packing list, and certificate of origin — is prepared to customs clearance standards for the destination country. A functional test report and certificate of conformance (CoC) are available upon request for procurement orders requiring quality documentation.

The 12-month warranty covers manufacturing defects and functional failure under normal operating conditions. Warranty claims are processed with a target response time of 48 hours; replacement units are dispatched before the defective unit is returned, subject to a deposit arrangement for qualified accounts.

Contact Information

Email: [email protected]
WhatsApp: +86 18359268345
Web: siemensplc.com
Location: Xiamen, China
© 2026 siemensplc.com. All rights reserved.