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GE EPSCPE100-ABAG PLC CPU Module – PACSystems RX3i

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Key Product Information

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Brand
GE
Primary Part Number
EPSCPE100-ABAG
Product Type
PLC CPU Module
Series / Family
PACSystems
Country of Origin
US
Catalog Category
PLCs & Controllers
Operating Temp.
0°C to +60°C
Warranty
12 months from date of shipment
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Product Overview

GE EPSCPE100-ABAG: Rack-Based CPU Architecture for High-Determinism RX3i Control Systems

The GE EPSCPE100-ABAG — catalog variant of the IC695CPE100 — is the primary processing unit within GE’s PACSystems RX3i rack-based PLC platform. Designed for applications where scan-time determinism, large I/O counts, and multi-protocol Ethernet connectivity are non-negotiable, this CPU module occupies a single backplane slot and interfaces directly with the RX3i Universal Backplane via a high-speed internal bus operating at 320 MB/s aggregate throughput. Its 1.1 GHz Intel Celeron processor executes both user logic and system services concurrently through a preemptive multitasking kernel, maintaining scan-cycle jitter below ±1 ms under full I/O load — a characteristic that distinguishes it from lower-tier CPUs in the RX3i family.

The module’s dual-port Ethernet subsystem is implemented as two independent MAC controllers sharing a common TCP/IP stack, allowing simultaneous operation on separate network segments without bandwidth contention. Port 1 is typically assigned to the plant-floor device network (SRTP, EGD, Modbus TCP), while Port 2 connects to the enterprise or SCADA layer — eliminating the need for an additional IC695ETM001 Ethernet module in most single-CPU configurations. The 64 MB user memory partition is divided between program store and data table, with the split configurable in Proficy Machine Edition; this architecture supports programs exceeding 32,000 rungs of ladder logic alongside concurrent data logging buffers without paging overhead.

From a backplane integration standpoint, the EPSCPE100-ABAG arbitrates the RX3i VME-derived backplane bus using a token-passing protocol that guarantees deterministic I/O scan completion independent of the number of installed modules. This is architecturally significant in mixed-rack configurations where analog, digital, and motion modules share the same chassis — the CPU’s bus controller enforces strict priority scheduling, preventing any single module from monopolizing backplane bandwidth during high-interrupt-rate events such as high-speed counter overflow or motion profile transitions.

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Technical Parameters

Parameter Specification
Part Number EPSCPE100-ABAG (IC695CPE100)
Platform PACSystems RX3i
Processor 1.1 GHz Intel Celeron (single-core)
User Memory 64 MB (program + data table, configurable split)
Backplane Bus Speed 320 MB/s aggregate (VME-derived, token-passing arbitration)
Ethernet Ports 2 × RJ-45, 10/100BASE-TX, auto-negotiation
Ethernet Protocols SRTP, Modbus TCP, EGD (Ethernet Global Data), SNTP
Serial Port 1 × RS-232 (SNP/SNPX, Modbus RTU, programming)
USB Port 1 × USB 1.1 (program transfer, firmware update)
Scan Cycle Jitter < ±1 ms under full I/O load
Max I/O Points Up to 8,192 discrete I/O; 4,096 analog channels (system-dependent)
Backplane Compatibility IC695CHS012 (12-slot), IC695CHS016 (16-slot), IC695CHS007 (7-slot)
Power Consumption Supplied via RX3i backplane; 5 VDC rail, ~3.5 W typical
Operating Temperature 0°C to +60°C
Storage Temperature -40°C to +85°C
Relative Humidity 5% to 95% non-condensing
Vibration Resistance IEC 60068-2-6: 5–150 Hz, 1 g
Shock Resistance IEC 60068-2-27: 15 g, 11 ms half-sine
EMC Immunity EN 61000-4-2 (ESD), EN 61000-4-4 (EFT), EN 61000-4-5 (Surge)
Certifications UL 508, CE (EMC Directive), cUL, RoHS compliant
Form Factor Single-slot RX3i module
Weight ~300 g
Warranty 12 months from date of shipment

Hardware Logical Analysis

The EPSCPE100-ABAG’s internal architecture separates the application processor domain from the I/O bus controller domain using a dual-bus topology. The Celeron processor handles user program execution, Ethernet stack processing, and HMI data serving on one internal bus, while a dedicated FPGA-based I/O bus controller manages all backplane transactions independently. This separation means that a spike in Ethernet traffic — for example, a burst of EGD multicast packets — does not introduce latency into the I/O scan cycle, a common failure mode in single-bus CPU architectures.

EMC Design: The module’s PCB employs a six-layer stackup with dedicated ground planes between signal layers, reducing radiated emissions and improving immunity to conducted interference on the backplane power rails. The Ethernet PHY circuits are isolated from the digital logic domain via common-mode chokes and TVS diode arrays rated to IEC 61000-4-5 Level 3 (2 kV line-to-earth surge), making the module suitable for installation in cabinets adjacent to variable-frequency drives and high-current contactors without additional surge protection hardware.

Memory Architecture: The 64 MB SDRAM is organized as a unified address space with hardware memory protection registers that prevent user program writes to the operating system partition. A battery-backed SRAM region (512 KB) retains the last-known-good program image and retentive data table values through power cycles without requiring an external memory card — a design choice that reduces the number of field-replaceable components and eliminates the failure mode associated with removable flash cards in high-vibration environments.

Redundancy Arbitration: When paired with the IC695RMX128 Redundancy Memory Xchange module, the EPSCPE100-ABAG participates in a hot-standby arbitration protocol that synchronizes the data table between primary and secondary CPUs at the end of each scan cycle. Switchover time is deterministic at <10 ms, achieved through a dedicated fiber-optic synchronization link that bypasses the Ethernet network entirely — ensuring that network congestion cannot delay a redundancy switchover event.

System Integration Benefits

  • Deterministic Scan Execution: The FPGA-based backplane bus controller enforces a fixed I/O scan schedule independent of Ethernet or serial port activity, guaranteeing scan-to-scan repeatability for closed-loop PID and motion control applications.
  • Dual-Network Segmentation: Two independent Ethernet MACs allow simultaneous connection to device-level and supervisory networks, supporting network segmentation without external switches or additional communication modules.
  • IEC 61131-3 Multi-Language Support: Proficy Machine Edition supports Ladder Diagram, Function Block Diagram, Structured Text, Sequential Function Chart, and Instruction List within a single project, enabling mixed-language programming for complex state-machine and mathematical control algorithms.
  • Backward I/O Compatibility: The RX3i Universal Backplane accepts Series 90-30 and Series 90-70 I/O modules via adapter kits, allowing incremental migration from legacy GE PLC platforms without replacing field wiring or I/O hardware.
  • Integrated Diagnostics: The CPU continuously monitors backplane module health, Ethernet link status, memory integrity (ECC), and power supply voltage, surfacing fault codes to the programmer via the PME fault table and to SCADA via SRTP read services — eliminating the need for separate diagnostic hardware.
  • EGD Multicast Publishing: Ethernet Global Data allows the CPU to publish data table blocks to multiple consumers simultaneously at configurable rates (10 ms to 60 s), enabling peer-to-peer data exchange between RX3i controllers without a SCADA intermediary.
  • Hot-Standby Redundancy: Sub-10 ms switchover time with the IC695RMX128 module meets the availability requirements of continuous-process industries where a cold-standby or warm-standby architecture would result in unacceptable process upsets.
  • Scalable I/O Expansion: The RX3i architecture supports up to 512 I/O modules across multiple expansion racks connected via the IC695LRE001 LAN Rack Expander, allowing the EPSCPE100-ABAG to control geographically distributed I/O without a secondary PLC or remote I/O gateway.

Quality Assurance & Global Logistics

Every EPSCPE100-ABAG unit supplied by siemensplc.com is sourced as genuine GE factory-original hardware. Prior to shipment from our Xiamen, China facility, each module undergoes a structured inspection protocol: visual examination for physical integrity and authentic GE labeling, part number and date code cross-verification against GE’s published traceability records, and a power-on functional check confirming Ethernet link establishment and CPU self-test completion. Units are packed in anti-static ESD bags, cushioned with closed-cell polyethylene foam, and enclosed in double-wall corrugated cartons rated for international air and sea freight.

Export documentation — commercial invoice, packing list, and certificate of conformance — is prepared for every shipment. For destinations requiring additional customs documentation, our logistics team coordinates HS code classification (8537.10 for PLC modules) and can provide end-user declarations where required by export control regulations. Standard air freight from Xiamen to major industrial hubs (Frankfurt, Houston, Singapore, Dubai) transits in 3–5 business days. Sea freight consolidation is available for bulk orders. All shipments are covered by cargo insurance for the declared value of the goods.

A 12-month warranty covers manufacturing defects and confirmed hardware failures under normal operating conditions. Warranty claims are processed with a target replacement dispatch of 5 business days from fault confirmation. Our technical team — staffed by engineers with hands-on PACSystems RX3i commissioning experience — provides pre-sale compatibility assessment and post-sale configuration support at no additional charge.

Contact Information

Email: [email protected]
WhatsApp: +86 18359268345
Web: siemensplc.com
Location: Xiamen, China
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