Mitsubishi A1SCPU PLC CPU Module – MELSEC-A Series

Mitsubishi A1SCPU – Compact CPU Module for MELSEC-A Series Discrete and Process Control

The A1SCPU occupies the zero-slot position of any MELSEC-A slim-series base unit (AnS family) and functions as the sole program execution engine for the entire rack. Its internal A-bus backplane interface operates at 5 VDC and arbitrates data exchange between the CPU and all downstream I/O, special-function, and communication modules through a synchronous, fixed-priority bus cycle. Unlike distributed-intelligence architectures, the A1SCPU centralizes all ladder-logic evaluation, timer/counter accumulation, and I/O image-table refresh within a single 16-bit processor core — a design choice that eliminates inter-node arbitration latency and guarantees deterministic scan-cycle completion under worst-case I/O loading.

Program execution follows a strict four-phase cyclic scan: Input Image Refresh → Ladder Program Execution → Output Image Refresh → END/Watchdog Reset. The watchdog timer is hardware-enforced; if any single scan cycle exceeds the configured limit, the CPU halts output and asserts a fault relay — a fail-safe behavior that prevents runaway actuator states in the event of software anomalies. At 0.8 µs per basic instruction, the A1SCPU sustains sub-10 ms scan times on programs up to 8K steps under typical I/O loading, making it suitable for conveyor sequencing, batch process control, and multi-axis coordinated motion at moderate speeds.

Memory architecture separates program storage from data registers at the silicon level. Program steps reside in battery-backed CMOS RAM, retaining ladder logic through power interruptions without requiring a memory cassette for base configurations. An optional memory cassette (A3NMCA-8 or A3NMCA-16) extends program capacity to 16K steps for larger applications. Data registers (D0–D1023), internal relays (M0–M2047), timers (T0–T255), and counters (C0–C255) are all battery-backed, preserving process state across unplanned shutdowns — a critical requirement in continuous-process industries where cold-restart initialization is operationally costly.

The RS-422 programming port on the CPU front panel supports direct connection to a PC running GX Developer or GX Works2 (A-series compatibility mode). Online program modification — inserting or deleting rungs while the CPU remains in RUN mode — is supported, enabling maintenance engineers to implement logic corrections without halting production. For networked topologies, MELSEC-NET/MINI-S3 or CC-Link master/slave modules mount in adjacent base slots and communicate with the CPU via the shared A-bus, extending the control domain to remote I/O stations up to 200 m away without additional CPU overhead beyond the network refresh time allocated in the scan cycle.

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Technical Parameters

Hardware Logical Analysis

Backplane Bus Arbitration: The A1SCPU implements a master-arbitrated A-bus protocol in which the CPU holds permanent bus mastership during normal operation. All I/O and special-function modules are passive slaves that respond only when addressed by the CPU’s bus controller. This eliminates bus contention entirely — there is no token-passing overhead, no collision-detection delay, and no probabilistic latency introduced by competing bus masters. The result is a fully deterministic I/O refresh time that scales linearly with the number of occupied slots, not with traffic volume.

EMC and Noise Rejection Design: The A1SCPU’s internal power rail is isolated from the backplane 5 VDC bus through a DC-DC converter stage with common-mode choke filtering. Signal lines between the CPU logic board and the bus connector are routed with controlled impedance and guarded by ground planes on both sides of the PCB stack. The front-panel RS-422 port uses differential signaling with ±7 V common-mode rejection, making it immune to ground-loop noise in long cable runs up to 50 m. Mitsubishi’s published noise immunity specification of 1,500 V p-p at 1 µs pulse width reflects conducted transient immunity consistent with IEC 61000-4-4 Level 3 criteria.

Fail-Safe Watchdog Architecture: The watchdog timer is implemented in dedicated hardware logic, independent of the main CPU core. If the CPU core fails to reset the watchdog within the configured scan-cycle window — due to infinite loops, stack overflow, or hardware fault — the watchdog asserts a hardware RESET signal that drives all output modules to their de-energized (safe) state before halting the CPU. This two-stage fault response (output de-energization precedes CPU halt) prevents the brief window of undefined output state that software-only watchdog implementations can produce.

Battery-Backed CMOS RAM Retention: Program and data memory are implemented in low-leakage CMOS SRAM with a dedicated lithium battery circuit. The battery circuit uses a diode-OR arrangement: when main power is present, the SRAM is powered from the regulated 5 VDC rail; when main power fails, the battery takes over within microseconds via the diode switchover, with no glitch on the SRAM supply rail. This architecture guarantees zero data corruption during power transitions — a requirement for applications where re-initialization from cold start is not operationally acceptable.

System Integration Benefits

• Deterministic Scan Cycle: Fixed-priority A-bus arbitration ensures I/O refresh completes within a bounded time window on every scan, enabling precise timing of output pulses and interlock logic without jitter accumulation.
• Zero-Overhead Network Extension: CC-Link and MELSEC-NET modules share the A-bus without consuming CPU instruction cycles; network refresh is handled by the communication module’s onboard processor, preserving CPU bandwidth for ladder execution.
• Online Program Modification: Rung insertion and deletion in RUN mode allow maintenance engineers to implement logic corrections during production without a controlled shutdown, reducing unplanned downtime to near zero for software-related changes.
• Granular Diagnostic Transparency: Special relays M9000–M9255 and special registers D9000–D9255 expose real-time CPU status — scan time, battery voltage, I/O error codes, and watchdog status — directly readable by ladder logic for integration into SCADA alarm systems.
• Modular I/O Scalability: The AnS base unit family supports 3 to 8 I/O slots per rack, with extension base units adding up to 256 total I/O points. Expansion requires no CPU firmware changes — the CPU auto-detects module types at power-on via the A-bus initialization handshake.
• Legacy System Longevity: GX Works2 compatibility ensures that engineering teams can maintain, modify, and document A1SCPU programs using a current, actively supported software platform without migrating to a new PLC family.
• Standardized Wiring Interface: All I/O modules in the MELSEC-A slim series use identical terminal block pitches and connector types, allowing I/O module substitution without rewiring field cables — a significant advantage during module replacement in live panels.
• Proven Mean Time Between Failures: The A1SCPU’s field deployment history across automotive, food processing, and utilities sectors spanning 20+ years provides empirical MTBF data that no accelerated lab test can replicate, giving procurement engineers confidence in long-term availability and reliability.

Quality Assurance & Global Logistics

Every A1SCPU unit supplied by siemensplc.com is sourced through verified industrial distribution channels with full batch traceability back to Mitsubishi Electric’s manufacturing records. Incoming inspection covers three stages: visual and label authentication against Mitsubishi Electric’s current genuine-product reference database; serial number format verification; and functional power-on test confirming CPU RUN-mode entry, LED status indication, and RS-422 port responsiveness.

Counterfeit screening is performed against known reference units held in our quality library. PCB layer count, component markings, and connector tolerances are cross-checked. Units that fail any single inspection criterion are quarantined and returned to the supply chain — zero-tolerance policy with no exceptions for expedited orders.

Shipping operations are based in Xiamen, China, with direct access to Xiamen Gaoqi International Airport and Xiamen Port, enabling same-day dispatch on confirmed orders received before 14:00 CST. Express courier options include DHL Express, FedEx International Priority, and UPS Worldwide Express, with typical transit times of 3–5 business days to Europe, North America, Southeast Asia, and the Middle East. Sea freight consolidation is available for bulk orders exceeding 50 units. All shipments include ESD-protective inner packaging, shock-absorbing foam inserts, and a double-wall outer carton rated to ISTA 2A drop-test standards. A tracking number is issued within 2 hours of dispatch.

The 12-month warranty covers manufacturing defects and functional failure under normal operating conditions. Warranty claims are processed within 3 business days of receipt of the returned unit, with replacement shipment or credit note issued upon confirmation of defect.

Contact Information

Email: [email protected]
WhatsApp: +86 18359268345
Web: siemensplc.com
Location: Xiamen, China
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