Mitsubishi A2ASCPU PLC CPU Module – MELSEC-A Series

Mitsubishi A2ASCPU CPU Module — Backplane Bus Architecture and Scan-Cycle Control Logic in MELSEC-A Series Systems

The A2ASCPU is the central processing unit of Mitsubishi Electric’s MELSEC-A (AnS) Series PLC platform. Within a distributed control architecture, this module occupies the CPU slot of an AnS-series base unit and assumes full authority over program execution, I/O refresh, inter-module communication via the backplane bus, and system diagnostics. Its role is not peripheral — every scan cycle, every device state transition, and every network data exchange in the control loop is orchestrated by this module’s internal execution engine.

The A2ASCPU executes ladder diagram and SFC (Sequential Function Chart) programs stored in its internal CMOS RAM, backed by a lithium battery (A6BAT). Program capacity is 14K steps, sufficient for mid-complexity sequencing applications. The CPU’s instruction set covers basic logic, comparison, arithmetic, data transfer, PID loop control, and high-speed counter interface — covering the majority of discrete and process control requirements without auxiliary co-processors.

The backplane bus of the AnS series operates as a parallel data bus connecting the CPU to all installed I/O and special function modules. During each scan cycle, the A2ASCPU performs a deterministic three-phase operation: (1) input refresh — reading all physical input states from I/O modules into the internal image register; (2) program execution — processing the ladder/SFC program against the current image register; (3) output refresh — writing computed output states back to I/O modules via the backplane. This fixed-cycle architecture eliminates non-deterministic latency introduced by interrupt-driven or event-based execution models, making the A2ASCPU suitable for synchronized multi-device sequencing where jitter tolerance is below 5 ms.

Communication with programming tools (GX Developer, GX Works2) is handled through the RS-232C port on the CPU front panel, using the SC-09 programming cable. The CPU also supports MELSECNET/MINI-S3 for peer-to-peer PLC networking in multi-CPU panel configurations, enabling shared device data exchange without dedicated communication modules in smaller topologies.

Real-time Stock & RFQ: [email protected] | WhatsApp: +86 18359268345

Technical Parameters

Hardware Logical Analysis

Backplane Bus Arbitration: The A2ASCPU acts as the sole bus master on the AnS backplane. All I/O and special function modules are bus slaves — they respond only when addressed by the CPU during the I/O refresh phase. This master-slave arbitration eliminates bus contention and guarantees that no module can corrupt the data bus during CPU program execution. The parallel bus architecture allows simultaneous data transfer across multiple module slots within a single refresh cycle, reducing the per-slot refresh overhead compared to serial fieldbus alternatives.

CMOS RAM with Battery Retention: Program and device data are stored in low-power CMOS static RAM. The A6BAT lithium battery maintains memory state during power outages without requiring a capacitor-based hold-up circuit. This design avoids the voltage-droop failure mode common in supercapacitor-backed systems, where extended outages can corrupt partially retained data. Battery voltage is monitored by the CPU’s internal supervisory circuit; a low-battery diagnostic flag (SP.BATTLOW) is raised in the special relay area before retention capacity is exhausted, giving maintenance personnel advance warning.

EMC Design and Noise Immunity: The A2ASCPU’s PCB layout follows Mitsubishi Electric’s internal EMC design standard, which includes ground plane partitioning between the logic domain and the backplane interface, decoupling capacitors at each power rail entry point, and signal line filtering on the RS-232C port. The module is rated for operation in environments with conducted and radiated interference levels consistent with IEC 61000-4-4 (EFT/Burst) and IEC 61000-4-5 (Surge) — typical of panels containing variable frequency drives, contactors, and high-current switching loads.

Watchdog Timer (WDT) Architecture: An independent hardware watchdog timer monitors scan cycle completion. If the CPU fails to reset the WDT within the configured scan time limit (default: 200 ms, adjustable), the WDT triggers a CPU STOP and sets the ERROR LED. This hardware-level fault detection operates independently of the main processor, ensuring that a software hang or infinite loop does not result in undetected frozen outputs — a critical safety behavior in interlock-dependent applications.

Instruction Pipeline: The A2ASCPU processes basic contact and coil instructions at approximately 0.2 µs per instruction. Applied instructions (MOV, arithmetic, comparison) execute in 1–10 µs depending on operand type. This execution rate yields a 1K-step scan time of approximately 0.2 ms, enabling 5 ms total scan cycles for programs up to 14K steps — adequate for most discrete manufacturing and process control loops with sensor update rates in the 10–100 ms range.

System Integration Benefits

• Deterministic Fixed-Cycle Execution: The three-phase scan (input refresh → program execution → output refresh) runs at a fixed, configurable cycle time. This eliminates variable latency from interrupt-driven architectures, allowing downstream motion controllers and HMI systems to synchronize data polling to a known CPU cycle boundary.
• Drop-in Compatibility with AnS Base Units: The A2ASCPU is mechanically and electrically compatible with all AnS-series base units (A1S38B, A1S52B, A1S65B). No rewiring or base unit replacement is required when substituting an A2ASCPU for an A2ACPU or A2UCPU in an existing panel, reducing maintenance downtime to module swap time only.
• Full AnS I/O Module Ecosystem: The CPU supports the complete range of AnS-series I/O modules — digital input/output (AX40S, AY40S), analog I/O (A68AD, A62DA), temperature input (A68TD), and high-speed counter (A1SD61) — without requiring firmware updates or parameter reconfiguration when modules are added or replaced.
• GX Developer / GX Works2 Programming: Both IEC 61131-3 compliant programming environments support the A2ASCPU natively. Ladder diagrams, SFC programs, and structured text blocks can be uploaded/downloaded via the RS-232C port. Online monitoring, forced I/O, and device batch monitoring are available without additional licensing.
• MELSECNET/MINI-S3 Peer Networking: The built-in MELSECNET/MINI-S3 interface allows up to 8 AnS-series PLCs to share device data (bit and word) across a dedicated network without occupying a base unit slot. This reduces BOM cost in multi-CPU panel configurations compared to solutions requiring dedicated network interface modules.
• Diagnostic Transparency via Special Relay/Register Area: The CPU exposes system status through a dedicated special relay (SM) and special register (SD) area. Fault codes, scan time measurements, battery voltage status, I/O module error flags, and network communication status are all readable from the ladder program or via GX Developer’s diagnostic screens — enabling structured fault isolation without external diagnostic hardware.
• Long-Term Spare Parts Availability: The MELSEC-A Series has been in production for over three decades. Mitsubishi Electric and authorized distributors maintain spare parts availability for legacy installed bases. The A2ASCPU is a high-demand spare for facilities that cannot migrate to iQ-R or Q Series without full panel redesign, making stock availability a procurement priority.
• Battery-Independent Program Retention Option: For applications where battery maintenance is operationally impractical, the A2ASCPU supports EEPROM memory cassette options (A3NMCA-□) that retain program data without battery power. This is particularly relevant for remote unmanned installations where periodic battery replacement cannot be scheduled.

Quality Assurance & Global Logistics

Every A2ASCPU unit dispatched from our Xiamen, China facility undergoes a structured pre-shipment verification process. Visual inspection confirms label authenticity, connector pin integrity, PCB surface condition, and absence of physical damage consistent with counterfeit or mishandled product. Firmware revision is verified against Mitsubishi Electric’s published documentation for the A2ASCPU production series. Where test equipment permits, a power-on self-test is conducted to confirm the CPU initializes without error codes and the RUN/ERROR LED sequence matches factory specification.

Units are packed in anti-static shielding bags with humidity indicator cards, placed in foam-lined cartons rated for IEC 60068-2-27 shock and IEC 60068-2-6 vibration levels encountered in air freight. Each shipment includes a packing list, certificate of conformance, and — on request — a third-party inspection report from a CNAS-accredited laboratory.

Standard international shipment is via DHL Express or FedEx International Priority from Xiamen Gaoqi International Airport, with typical transit times of 3–5 business days to Europe, North America, Southeast Asia, and the Middle East. Sea freight LCL/FCL is available for bulk orders. All export documentation, including HS code classification (8537.10) and origin certificates, is prepared by our in-house trade compliance team.

A 12-month warranty covers manufacturing defects and functional failures under normal operating conditions. Warranty claims are processed with a replacement-first policy — a replacement unit is dispatched upon receipt of the defective module, minimizing production downtime for the customer.

Contact Information

Email: [email protected]
WhatsApp: +86 18359268345
Web: siemensplc.com
Location: Xiamen, China
© 2026 siemensplc.com. All rights reserved.