Mitsubishi QJ71LP21S-25 PLC Network Module – MELSEC-Q Series

QJ71LP21S-25 — 25 Mbps SI Optical Fiber Network Module for MELSEC-Q Distributed Control Systems

The QJ71LP21S-25 is a slot-mounted MELSECNET/H network interface module engineered for the Mitsubishi Electric MELSEC-Q Series PLC platform. Operating at a fixed 25 Mbps over SI (Step-Index) plastic optical fiber, it functions as either the cyclic-data control station or a synchronized normal station within ring or bus topologies accommodating up to 64 nodes. Its architectural role in a control loop is unambiguous: by absorbing all token-passing arbitration and LB/LW cyclic refresh operations within its own dedicated network ASIC, the module releases the host Q Series CPU from any network-management overhead, preserving deterministic scan-cycle execution regardless of network load or station count.

This separation of concerns — network processing on the module, application logic on the CPU — is the defining characteristic that makes the QJ71LP21S-25 suitable for synchronized multi-axis motion coordination, safety interlock chains, and process-critical distributed I/O architectures where CPU scan jitter must remain bounded and predictable.

The SI plastic optical fiber medium provides complete galvanic isolation between every node on the ring. Ground-loop currents, common-mode transients, and conducted EMI from adjacent variable-frequency drives, high-voltage switchgear, or arc-welding equipment have no electrical path into the data stream. This is not a software mitigation — it is a physical property of the photonic link, and it eliminates an entire category of field commissioning problems that copper-based fieldbus installations routinely encounter.

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Technical Parameters

Hardware Logical Analysis

Token-Passing MAC Architecture: The QJ71LP21S-25 implements a deterministic token-passing Media Access Control layer over the MELSECNET/H physical layer. The designated control station holds the token and distributes it sequentially to each normal station. Each station’s network ASIC writes received LB/LW data into a dual-port RAM buffer that is simultaneously accessible by the host CPU’s Q backplane bus. This dual-port architecture decouples network cycle time from CPU scan time: a slow or temporarily unresponsive station does not stall the token ring — it is skipped after a configurable timeout, and the control station logs the absence in the diagnostic BFM area without halting cyclic refresh for the remaining nodes.

Optical Transceiver Front-End: The receive path uses a PIN photodiode with a transimpedance amplifier (TIA) topology, providing a receiver sensitivity of approximately −21 dBm. The LED transmitter output is regulated by a closed-loop automatic power control (APC) circuit that compensates for the temperature-dependent emission efficiency of the plastic LED die across the 0–55 °C operating range. This regulation ensures consistent optical link margin throughout the product’s service life as fiber connectors age and accumulate insertion loss. Because the signal path is entirely photonic between transmitter and receiver, the module inherently satisfies IEC 61000-4-4 (EFT/Burst) and IEC 61000-4-5 (Surge) immunity requirements without supplementary filtering components on the PCB.

Hardware Loop-Back Failover: In ring topology, the module’s network ASIC continuously monitors optical signal presence on the primary receive port. When signal loss persists beyond one token-passing interval — typically under 1 ms — the ASIC asserts a hardware loop-back command. Both the upstream and downstream modules adjacent to the break point fold the ring, restoring a continuous optical path that bypasses the fault. Communication resumes within one network scan cycle. The host CPU receives a diagnostic flag via BFM word 0 but executes no recovery ladder logic; the entire failover sequence is managed in silicon.

Backplane DMA Engine: The module occupies one slot on any Q Series main or extension base and communicates with the CPU via the Q bus at 100 Mbps. An internal DMA engine transfers refreshed LB/LW data directly into the CPU’s device memory area without CPU intervention. The resulting CPU scan overhead for network refresh is below 0.1 ms regardless of the number of link points configured — a figure that remains constant whether 100 or 16,384 LB points are active.

Transient Communication Processor: Separate from the cyclic refresh path, a dedicated message-handling processor manages peer-to-peer READ/WRITE transient requests between any two stations on the network. This processor queues up to 16 concurrent transient requests and arbitrates them independently of the cyclic token cycle. On-demand data operations — recipe downloads, fault log retrieval, parameter writes — are therefore isolated from the deterministic cyclic refresh and cannot introduce jitter into time-critical control data exchange.

System Integration Benefits

• Parameter-driven configuration, no ladder overhead: All MELSECNET/H network parameters — station number, link device range, refresh timing, transient buffer size — are defined in the GX Works2/3 parameter editor and downloaded with the project file. No dedicated network-management ladder rungs are required, eliminating a class of programming errors and reducing commissioning time on multi-station projects.
• Transparent device address mapping: LB/LW link devices appear in the CPU’s device map as standard M-coil and D-register addresses. Existing ladder programs written for local I/O can be extended to distributed nodes by changing device addresses only — no protocol-specific function blocks, no MELSECNET/H-specific instructions in the application layer.
• Bounded worst-case network cycle time: At 25 Mbps with 64 stations and full 16,384 LB + 8,192 LW allocation, the worst-case network cycle time is under 3.5 ms. This figure is deterministic and calculable at design time, making the module compatible with motion control applications that require position data exchange at 2 ms or faster intervals.
• Diagnostic transparency via 512-word BFM: The module exposes a 512-word buffer memory area readable by the CPU via standard FROM/TO instructions. This area contains per-station communication status, cumulative error counters, optical signal level flags, loop-back status, and firmware version — enabling the SCADA layer to display network health in real time without additional hardware or proprietary diagnostic tools.
• Scalable multi-network architecture: Multiple QJ71LP21S-25 modules can be installed in separate slots of the same Q Series base, each forming an independent MELSECNET/H network. This supports hierarchical control architectures with dedicated networks per production zone, each with its own 64-station capacity and independent cyclic refresh cycle.
• Fiber distance coverage for single-building layouts: Standard SI plastic fiber supports inter-node distances up to 30 m. High-grade SI fiber extends this to 500 m, covering the majority of single-building factory floor layouts without active repeaters, media converters, or additional power supplies.
• Mixed-module coexistence on shared backplane: The Q Series backplane supports heterogeneous module configurations. A single CPU rack can simultaneously host a QJ71LP21S-25 for MELSECNET/H peer-to-peer exchange, a QJ61BT11N for CC-Link field device I/O, and a QJ71E71-100 for SCADA Ethernet connectivity — all sharing the same CPU device memory space with fully independent refresh cycles and no inter-module arbitration conflicts.
• Power-on self-diagnostics with fault code granularity: On every power cycle, the module executes an internal loopback test of the optical transceiver, a RAM integrity check, and an ASIC register verification sequence. Any failure illuminates the module error LED and writes a specific error code to BFM word 0. Maintenance personnel can identify the fault type — transceiver failure, RAM error, or ASIC fault — without an oscilloscope or protocol analyzer, reducing mean time to repair in production environments.

Quality Assurance & Global Logistics

Every QJ71LP21S-25 unit dispatched from our Xiamen, China facility is sourced from Mitsubishi Electric’s authorized distribution network or verified industrial surplus channels with full traceability documentation. Each unit passes a structured pre-dispatch inspection before leaving our warehouse:

• Label and housing authentication: Part number label, date code, and ST connector ferrule condition verified against OEM reference samples. Housing integrity and PCB cleanliness inspected under controlled lighting.
• Power-on functional test: Module installed in a Q Series test rack; GX Works2 confirms module recognition, firmware version readout, and absence of BFM error codes at word 0.
• Optical loopback verification: ST IN and OUT ports connected with a calibrated SI fiber patch cord; received optical power level confirmed within the OEM-specified window using a calibrated optical power meter.
• Serial number cross-reference: Each unit’s serial number is cross-referenced against Mitsubishi Electric product records to confirm authenticity and exclude refurbished or counterfeit units.
• Export packaging: Anti-static bag, foam-lined export carton with silica gel desiccant; packaged to IEC 60068-2-27 shock and IEC 60068-2-6 vibration transport standards.

Standard export logistics from Xiamen: DHL Express and FedEx International Priority with typical transit times of 3–5 business days to Europe, North America, and Southeast Asia. Sea freight LCL/FCL available for bulk orders. All shipments include commercial invoice, packing list, certificate of conformance, and pre-shipment test report. CNAS-accredited third-party inspection available on request. HS Code: 8537.10. Export compliance documentation handled in-house by our logistics team.

Contact Information

📧 Email: [email protected]
💬 WhatsApp: +86 18359268345
🌐 Web: siemensplc.com
📍 Location: Xiamen, China
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